10. The equipment as recited in declare 5 wherein the very first instruction is actually a load instruction, and wherein the load instruction passes the replay stage When the load instruction misses in a knowledge cache.
The detection of fill information currently being returned may be a sign from the info cache 30 or maybe the source of the fill data (e.g. the bus interface device 32) that fill info is currently being offered. In such cases, the sign is not really specific to the particular load overlook that brought about the recurring replay. The fill info might essentially be for an additional load miss out on. In these types of an embodiment, replay might be detected once more just after issuing Guidance in response for the fill signal. Instruction difficulty may well however be inhibited right until fill facts is returned. In other embodiments, a tag pinpointing the load skip leading to the replay can be used to establish the fill knowledge equivalent to the load overlook.
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The miss indicator may suggest cache misses (one for each load/retail outlet device 26A-26B). The fill indicator may possibly suggest that fill facts is returning (which may involve a sign in the sign-up selection for which fill facts is remaining returned). Alternatively, the fill sign may very well be furnished by the bus interface device 32 or almost every other circuitry. Every of execution units 22A-22B, 24A-24B, and 26A-26B could suggest if an instruction ordeals an exception utilizing the corresponding exception indicator. The replay sign might be supplied by the fetch/decode/challenge device fourteen if a replay problem is detected for an instruction.
Should the instruction is not staying picked for the load/keep pipeline (i.e. the instruction is remaining selected for that integer pipeline), then the resource registers with the instruction usually are not checked in opposition to the integer concern scoreboard 44A (decision block eighty, “no” leg) and the instruction may very well be eligible for challenge (assuming other issue constraints are met—block eighty four).
In reaction to your replay or redirect resulting from department misprediction, The problem Manage circuit forty two may well duplicate the contents in the integer replay scoreboard 44B for the integer problem scoreboard 44A. On this manner, the updates on the integer difficulty scoreboard 44A resulting from Recommendations which have been issued but canceled as a result of replay might be deleted. On top of that, the point out in the scoreboard for Recommendations which weren't canceled (Those people beyond the replay stage) could possibly be retained. In the same way, in reaction to an exception, The problem Manage circuit 42 may copy the contents of the integer graduation scoreboard 44C to both equally the integer replay scoreboard 44B and also to the integer situation scoreboard 44A.
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If a floating issue load instruction can be a pass up (determination block one hundred ten), the issue control circuit 42 sets the bit to the location register on the floating level load within the FP Uncooked Load replay scoreboard 46A (block 112). If a floating level load pass up is passing the graduation phase (final decision block 114), The problem Command circuit 42 sets the bit to the place register with the floating level load in the FP RAW Load graduation scoreboard 46B (block 114). In reaction to issuing a floating point instruction into among the list of floating place pipelines (conclusion block 118), the issue Manage circuit 42 sets the bit for your desired destination sign up with the floating place instruction in Each and every on the FP EXE RAW issue scoreboard 46C, the FP Madd Uncooked issue scoreboard 46E, the FP EXE WAW issue scoreboard 46G, plus the FP Load WAW challenge scoreboard 46I (block 120).
6. The apparatus as recited in assert 5 wherein the Command circuit is configured to selectively inhibit issuance of a 3rd instruction depending on which of the plurality of pipelines to which the 3rd instruction is to be issued if the 1st scoreboard indicates a generate pending to among the operands in the third instruction.
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FIGS. 6-9 are flowcharts illustrating the operation of 1 embodiment of The problem control circuit forty two with the integer scoreboards and integer instruction challenge. Normally, the circuitry represented by FIGS. 6-9 might pick which pipe phase an instruction is in by examining the pipe point out in the corresponding entry of the issue queue 40. Considered in read more yet another way, the circuitry represented by a presented conclusion block may perhaps decode the sort area in Each and every entry and also the corresponding pipe point out to detect if an instruction in any concern queue entry is really an instruction in the pipe phase looked for by That call block.
It's noted that, for embodiments employing the pipeline shown in FIG. 3, the limited floating position Guidelines are eight clock cycles from the Wr stage at challenge.